1 product information cml semiconductor products FX029 features 2 digitally controlled amplifiers gain/attenuation range of 48db + output mute, in 2db steps gain/attenuation levels set by serial interface separate fixed-gain uncommitted amplifier 5 volt low-power operation applications cellular and pmr communications systems automatic and manual test equipment remote gain adjustments telephone audio settings medical equipment audio and data gain setting applications brief description the FX029 single-chip dual digitally controlled amplifier array can replace manual audio-level controls in most electronic applications including radio and line communications systems. the FX029 comprises two digitally controlled gain and attenuation stages, with each stage having 48 distinct gain steps (range; between -48db and +48db in 2db steps) plus a mute state to powersave the addressed section. minimum current drain results from muting both sections. both gain stages have selectable inputs. this switching allows for selection of three different input signals to stage 1 and two to stage 2. dual digitally controlled amplifier array publication d/029/3 april 1997 provisional issue FX029 fig.1 functional block diagram stage 1 also provides output switching. in addition to the two digitally controlled gain stages, there is a general purpose, uncommitted inverting amplifier; the gain of this particular amplifier is component controlled externally using negative feedback. control of each gain stage section is accomplished through the serial interface. all switching is accomplished using controlled rise and fall times, thereby ensuring no annoying transients (clicks or pops). the FX029 requires a single 5 volt supply and is available in compact cerdip and small outline packages. 3 2 1b 1a v dd v bias v ss stage 1 stage 1 inputs stage 2 inputs stage 3 input outputs control 1 control 1 gain v bias v bias v ss v ss gain serial clock serial data control 2 control 2 v bias 6 6 stage 2 - + in 2a in 1a in 2b in 1b in 3 in 1c (uncommitted) stage 3 serial interface stage 1 control register stage 2 control register load/latch
2 serial clock: this external clock input is used to clock in the control data. see figure 4 for timing information. this input has an internal 1m w pullup resistor. serial data: operation of the two amplifier stages (1 and 2) is controlled by the data entered serially at this pin. the data is entered (bit 13 to bit 0) on the rising edge of the external serial clock. the data format is described in tables 1-3 and figure 4. this input has an internal 1m w pullup resistor. load/latch: governs the loading and execution of the serial control data. during serial data loading this input should be kept at a logical 1 to ensure that data rippling past the latches has no effect. when all 14 bits have been loaded this input should be strobed 1 to 0 to 1 to latch the new data in. data is executed on the rising edge of this strobe. in 1a (stage 1 input 1) : analogue input. in 1b (stage 1 input 2) : analogue input. in 2a (stage 2 input 1) : analogue input. in 2b (stage 2 input 2) : analogue input. v ss : negative supply rail (gnd). v bias : the output of the on-chip bias circuitry, held at v dd /2. in 1c (stage 1 input 3) : analogue input. normally used for fsk data. out 2 (stage 2 output) : analogue output. out 1b (stage 1 output 2) : analogue output. out 1a (stage 1 output 1) : analogue output. out 3 (uncommitted amplifier output) : output from the general purpose uncommitted amplifier. in 3 (uncommitted amplifier input) : inverting input to general purpose uncommitted amplifier. v dd : positive supply rail. a single +5-volt power supply is required. pin number function dw/j 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 d5 1 4 5 6 7 8 9 12 13 16 17 18 20 21 23 24 FX029
3 application information external components fig.2 recommended external components 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 serial clock in 1a in 1b in 2a in 2b in 1c out 2 out 1b out 1a out 3 in 3 v bias v ss v ss v ss v dd v dd c 1 c 2 c 3 c 4 c 5 c 7 serial data load/latch FX029 dw/j serial clock serial data t t t t pwl pwh ds t llw t lld t llo dh load/latch d0 1st clock pulse 14th clock pulse d13 d12 d1 serial interface timing component recommendations component value c 1 0.1 m f c 2 0.1 m f c 3 0.1 m f c 4 0.1 m f c 5 0.1 m f c 6 not used c 7 1.0 m f tolerances 20% input capacitors c 1 to c 5 are only required for ac input signals; dc input signals do not require these components. the gain of the uncommitted stage (3) is set by external components employed around the input and output pins (see specification page). application recommendations to avoid noise and instability the following practices are recommended: (a) use a clean, well-regulated power supply. (b) keep tracks short. (c) inputs and outputs should be shielded wherever possible. (d) analogue tracks should not run parallel to digital tracks. (e) a ground plane connected to v ss will assist in eliminating external pick-up on the channel input and output pins. (f) avoid running high level outputs adjacent to low level inputs. (g) the serial clock should not be running consecutively when not in the process of actually loading data. fig.3 serial timing diagram - see specification page for timing specifications
4 control data and timing the gain and i/o signal path for each section (channels 1 and 2) is set individually by a 14-bit data word (d0 to d13). data is loaded on the rising edge of the serial clock. loaded data is executed on the rising edge of the load/ latch pulse.the 14-bit word consists of 1 channel address bit (d7) for selection of the channel to be programmed, 6 bits for setting the amplification/attenuation level (d8-d13), 3 bits for input selection (d4 and d6), and 4 bits for output settings (d0-d3). this format is illustrated below in figure 4. tables 1-3 show how the data word is used to control channel selection, amplification/attenuation, input selection and output settings, respectively. gain/attenuation level input select channel address output settings d13 d12 d12 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 fig.4 level-controlling data word format d13 d12 d11 d10 d9 d8 gain set (db) 0 0 0 0 0 0 mute 000001 -48 000010 -46 000011 -44 000100 -42 000101 -40 000110 -38 000111 -36 001000 -34 001001 -32 001010 -30 001011 -28 001100 -26 001101 -24 001110 -22 001111 -20 010000 -18 010001 -16 010010 -14 010011 -12 010100 -10 010101 -8 010110 -6 010111 -4 011000 -2 011001 0 table 1 - amplification/attenuation level d13 d12 d11 d10 d9 d8 gain set (db) 011001 0 011010 2 011011 4 011100 6 011101 8 011110 10 011111 12 100000 14 100001 16 100010 18 100011 20 100100 22 100101 24 100110 26 100111 28 101000 30 101001 32 101010 34 101011 36 101100 38 101101 40 101110 42 101111 44 110000 46 110001 48 110010 48 110011 48 d7 stage d6 d5 d4 inputs selected selected 0 1 0 0 0 none 1 2 001 1 010 2 0 1 1 1 and 2 100 3 1 0 1 1 and 3 1 1 0 2 and 3 1 1 1 1, 2 and 3 table 2 stage and input selection d3 d2 output d1 d0 outputs 1b 1a & 2 0 0 high z 0 0 high z 0 1 enabled 0 1 enabled 10 v ss 10 v ss 11 v bias 11 v bias table 3 stage output selection
5 specification absolute maximum ratings exceeding the maximum rating can result in device damage. operation of the device outside the operating limits is not implied. supply voltage -0.3 to 7.0v input voltage at any pin (ref. v ss = 0v) -0.3 to (v dd + 0.3v) sink/source current (supply pins) +/- 30ma (other pins) +/- 20ma total device dissipation (dw/j) @ t amb 25c 800mw max. (d5) @ t amb 25c 550mw max. derating (dw/j) 10mw/c (d5) 9mw/c operating temperature range: FX029dw/d5/j -40c to +85c storage temperature range: FX029d5 -40c to +85c FX029dw/j -55c to +125c operating characteristics all device characteristics are measured under the following conditions unless otherwise specified: v dd = 5.0v, t amb = 25c. external components as figure 2. audio 0db ref. = 775mvrms characteristics see note min. typ. max. unit supply voltage 4.5 5.0 5.5 v current (all stages mute) - 0.10 - ma (all stages operating) - 3.0 - ma digital inputs 4 input logic 1 3.5 - - v input logic 0 - - 1.5 v digital input impedances 0.5 1.0 - m w gain control amplifier stages (stages 1 and 2) bandwidth (-3db) 1 3.3 - - khz output impedance - 1.0 2.0 k w total harmonic distortion 2, 5 - 0.35 0.5 % interstage isolation - 60.0 - db gain 46.0 48.0 - db attenuation 46.0 48.0 - db gain/attenuation step size - 2.0 - db/step step error - - 0.4 db input impedance 50.0 - - k w input referred offset voltage (v ios ) - 10.0 - mv uncommitted amplifier (stage 3) bandwidth (-3db) 3 10.0 - - khz output impedance - 1.0 2.0 k w total harmonic distortion 3 - 0.35 0.5 % open loop dc gain - 60 - db timing (see figure 3) serial clock high pulse width (t pwh ) 250 - - ns serial clock low pulse width (t pwl ) 250 - - ns data set-up time (t ds ) 150 - - ns data hold time (t dh ) 50.0 - - ns load/latch delay (t lld ) 200 - - ns load/latch over-time (t llo )--0ns load/latch pulse width (t llw ) 150 - - ns serial data clock frequency - - 2.0 mhz notes 1. gain set to maximum (+48.0db). 2. gain set 0db. input level 1.0khz, -3.0db (549mvrms). 3. gain externally set to 10.0db. 4. serial clock, serial data and load/latch inputs. 5. with a 100k w load on the relevant output.
6 package outlines the FX029 is available in the package styles outlined below. mechanical package diagrams and specifications are detailed in section 10 of the data book. pin 1 identification marking is shown on the relevant diagram and pins on all package styles number anti-clockwise when viewed from the top. handling precautions the FX029 is a cmos lsi circuit which includes input protection. however precautions should be taken to prevent static discharges which may cause damage. cml does not assume any responsibility for the use of any circuitry described. no circuit patent licences are implied and cml reserves the right at any time without notice to change the said circuitry. ordering information FX029d5 24-pin plastic s.s.o.p. FX029dw 16-pin plastic s.o.i.c. (d4) FX029j 16-pin cerdip (j2) not to scale max. body length 10.49mm max. body width 7.59mm not to scale max. body length 19.48mm max. body width 7.39mm FX029dw 16-pin plastic s.o.i.c. (d4) FX029j 16-pin cerdip dil (j2) FX029d5 24-pin plastic s.s.o.p. not to scale max. body length 8.33mm max. body width 5.38mm
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